CHAKRADHAR IPPILI

[email protected] • +91-8500590074 • Bangalore, Karnataka

PROFESSIONAL SUMMARY

9+ years of experience in the VLSI Design for Test (DFT) Working in DEFT Semiconductors form Oct 2018 till date, as Lead DFT Engineer Worked in Adeptchip services from July 2016 to Sep 2018, as DFT Engineer Collaborated with several clients, including Western Digital, Qualcomm and Samsung Semiconductor India Research (SSIR) Handled around 9 complex ASIC based SoC’s Worked on Scan Insertion, ATPG, MBIST/BSCAN Insertion & pattern generation, DFT logic synthesis, Scan pattern simulations with and without annotation, Logic equivalence check, Test coverage analysis, Tester pattern support for ASICs(Post silicon validation) and developing scan constraints for STA Worked on 4nm, 5nm, 16nm, 20nm, 28nm, 45nm technologies Extensively worked on Scan Architecture definitions and methodologies, defining low power DFT techniques, analyzing and fixing DRC’s, MBIST Insertion, Formal verification, JTAG,IJTAG, Simulations, timing closure analysis in PT & Tempus sessions, writing SDCs, tester pattern delivery support and debug silicon failures.

WORK EXPERIENCE

Lead DFT Engineer
10/2018 - Present
DEFT Semiconductors , Bangalore, Karnataka
• Performed Scan Insertion for SOC & Block levels using DFT Compiler
• Worked on compression techniques, to decide no of scan in & scan out ports required, OCC insertion & Wrapper cell insertion
• Analyzed all critical DRC’s and clean-up for both Scan Insertion and ATPG
• Responsible to resolve Scan Insertion/ATPG/Simulation flow/design related issues and team issues
• Test point insertion to improve coverage & reduce pattern count using SpyGlassDFT
• Developed & delivered the timing constraints to STA team for all modes of DFT
• Performed LEC at multiple stages, PRE DFT & POST DFT Netlists. Post DFT & Post PNR Netlists
• Analyzed different scenarios about dedicated, shared wrapper cells insertion, shared wrapper cells with different threshold levels
• Pattern generation for top level logic & SoC coverage analysis
• Re-targeting the patterns to SOC level using block level patterns in SA, TD, Bridging & XTOL modes using Testmax
• Validated the preamble sequence for all DFT modes by programming JTAG registers
• Performing Zero delay & Timing simulations from Blocks & Top
• Debugging the failures in both Zero delay & Timing Simulations
• Supported for Post Silicon scan pattern validations & yield improvement analysis(LVCC) on ATE
DFT Engineer
07/2016 - 09/2018
Adeptchip Services , Bangalore, Karnataka
• Top level Scan insertion using DFT Compiler
• Worked on Top level & Block level Scan insertion using DFT Compiler
• Worked on compression techniques, to decide no of scan in & scan out ports required
• Patten generation for blocks & Coverage analysis
• Re-targeting the patterns to SOC level using block level patterns in both SA & TD modes using Tetramax
• Debugging the failures in both Zero delay & Timing Simulations
• Delivered the timing constraints to STA team for all modes of DFT
• Performing LEC between PRE DFT & POST DFT Netlists
• Generated FSDB’s based on clock domain for IR analysis
• Analyzed PT sessions to debug Timing simulation failures
• Performed Logic and Timing ECO implementation

EDUCATION

B.Tech Electronics and communications Engineering
01/2015
Sri Sivani Institute Of Technology, JNTU University Kakinada, Andhra Pradesh , Andhra Pradesh

SKILLS

PROJECTS

Project 1
Technologies: DFT Compiler, Testmax, VCS simulator, Formality
• Performed Scan Insertion for SOC & Block levels using DFT Compiler
• Worked on compression techniques, to decide no of scan in & scan out ports required, OCC insertion & Wrapper cell insertion
• Analyzed all critical DRC’s and clean-up for both Scan Insertion and ATPG
• Responsible to resolve Scan Insertion/ATPG/Simulation flow/design related issues and team issues
• Test point insertion to improve coverage & reduce pattern count using SpyGlassDFT
• Developed & delivered the timing constraints to STA team for all modes of DFT
• Performed LEC at multiple stages, PRE DFT & POST DFT Netlists. Post DFT & Post PNR Netlists
• Analyzed different scenarios about dedicated, shared wrapper cells insertion, shared wrapper cells with different threshold levels
• Pattern generation for top level logic & SoC coverage analysis
• Re-targeting the patterns to SOC level using block level patterns in SA, TD, Bridging & XTOL modes using Testmax
• Validated the preamble sequence for all DFT modes by programming JTAG registers
• Performing Zero delay & Timing simulations from Blocks & Top
• Debugging the failures in both Zero delay & Timing Simulations
• Supported for Post Silicon scan pattern validations & yield improvement analysis(LVCC) on ATE
Project 2
Technologies: DFT Compiler, Tetramax, VCS simulator, Formality
• Top level Scan insertion using DFT Compiler
• Worked on Top level & Block level Scan insertion using DFT Compiler
• Worked on compression techniques, to decide no of scan in & scan out ports required
• Patten generation for blocks & Coverage analysis
• Re-targeting the patterns to SOC level using block level patterns in both SA & TD modes using Tetramax
• Debugging the failures in both Zero delay & Timing Simulations
• Delivered the timing constraints to STA team for all modes of DFT
• Performing LEC between PRE DFT & POST DFT Netlists
• Generated FSDB’s based on clock domain for IR analysis
• Analyzed PT sessions to debug Timing simulation failures
• Performed Logic and Timing ECO implementation
Project 3
Technologies: DFT Compiler, Tetramax, NC simulator, Formality
• Hierarchal Scan insertion using DFT Compiler
• Worked on SOC level & Block level Scan insertion using DFT Compiler
• Analyzed SOC level clocking structures and programming of PLL’s, verified PLL’s generated expected frequencies
• Patten generation for blocks & Coverage analysis
• Stuck-at & At-speed Pattern generation from Top in both (Intest & Extest Modes)
• RAM-Sequential pattern generation for TOP
• Debugging the failures in both Zero delay & Timing Simulations
• Delivered the timing constraints to STA team for all modes of DFT
• Performing LEC between PRE DFT & POST DFT Netlists
• Converting the ATPG patterns to ATE supportable format (ATP) & Pattern Delivery
• Worked on post silicon validation & diagnosis flow to debug post silicon failures

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