KANCHI TEJASWI

[email protected] • +91-8328568877 • Bangalore, India
LinkedIn: www.linkedin.com/in/kanchi-tejaswi

PROFESSIONAL SUMMARY

M.Tech graduate from IIT Kanpur with proven expertise in GPU architectures, ASIC and FPGA design, and hardware development, strengthened by hands-on industry and academic experience. Currently working at Volvo Eicher Commercial Vehicles Ltd. on automotive ECU design, cybersecurity validation, and hydrogen vehicle architecture, where I achieved a 20% improvement in early bug detection through emulator-based ECU testing. Skilled in RTL design, micro-architecture, SOC design, verification (UVM), PCB design, and timing analysis, with successful implementation of projects such as a 66% PCB size reduction for a PID-based diode laser temperature controller and development of an asynchronous FIFO with CDC verification. Certified in Digital IC Design and GPU Architectures & Programming, with strong foundations in CMOS/VLSI design, logic synthesis, and high-performance computing. Seeking roles as a GPU/ASIC Design Engineer or Hardware Development Engineer to apply technical depth, analytical problem-solving, and innovation in semiconductor and computing domains.

WORK EXPERIENCE

Deputy Manager - Product Digitalization
01/2025 - Present
Volvo Eicher Commercial Vehicles Ltd. , Indore, Madhya Pradesh, India
• Led penetration testing of automotive ECUs using advanced tools including Vector CANoe, ETAS INCA, and emulator-based platforms, executing comprehensive cybersecurity risk assessments aligned with ISO 21434 and ISO/SAE 21489 standards; improved early bug detection by 20%, significantly reducing downstream debugging costs and enhancing vehicle security posture
• Spearheaded the design and development of the Body Control Module (BCM), an ECU managing critical body functions such as lighting, wipers, and locking systems, resulting in a 15% increase in system automation and a measurable boost in vehicle intelligence and operational efficiency
• Directed hardware-software validation and compliance testing of ECU designs, ensuring seamless integration within vehicle architecture and strict adherence to ISO 26262 functional safety standards, which decreased integration defects by 25%
• Collaborated closely with a cross-functional team of 6 engineers across hardware, software, and cybersecurity domains to accelerate ECU development cycles by 18%, while expanding validation coverage and improving overall product quality

EDUCATION

M.Tech
07/2022 - 07/2024
Indian Institute of Technology, Kanpur , Kanpur, Uttar Pradesh, India GPA: 7.5
B.Tech
07/2017 - 07/2021
Sri Venkateswara University , Tirupati, Andhra Pradesh, India GPA: 8.12
Senior Secondary
07/2015 - 07/2017
Board of Intermediate Education, AP , Tirupati, Andhra Pradesh, India GPA: 96.8%
Secondary
07/2014 - 07/2015
Board of Secondary Education, AP , Puttur, Andhra Pradesh, India GPA: 9.8

SKILLS

Technical Skills: RTL Design, ASIC Design, FPGA Design, Micro-architecture, GPU Design, SOC Design, Design for Testability, Logic Synthesis, Hardware Verification, UVM Testbenches, Timing Analysis, CDC Verification
Soft Skills: Leadership, Team Collaboration, Problem Solving, Adaptability, Technical Documentation, Cross-functional Communication
Tools: ModelSim, Questa, Xilinx Vivado, Cadence Genus, Cadence Innovus, Synopsys Design Compiler, Mentor Graphics QuestaSim, LTspice, Altium Designer, Vector CANoe, ETAS INCA, Emulators
Other: Floor Planning, PCB Design, Hardware Architecture, Industry Standards ISO 21434, Industry Standards ISO/SAE 21489, Industry Standards ISO 26262, Cybersecurity Testing of ECUs, VLSI Methodologies

PROJECTS

Temperature Controller circuit - PCB (Printed Circuit Board) design and implementation
Technologies: Altium Designer, LTspice, Oscilloscope, Multimeter, PID Control Algorithms, Peltier Thermal Modules
• Developed and implemented a PID-based temperature control system integrating a Peltier module to achieve precise diode laser temperature stabilization, enhancing system reliability by reducing thermal fluctuations by over 15% and improving device uptime
• Designed and optimized compact PCB layouts for through-hole and SMD components using Altium Designer, achieving a 66% reduction in board size (final dimensions: 10cm × 10.5cm) while maintaining signal integrity, effective thermal dissipation, and manufacturability
• Reduced PCB design errors by 80% through iterative LTspice simulations, rigorous debugging, and enhanced design verification, accelerating development cycles and increasing first-pass fabrication success rate
• Created comprehensive schematics, Bill of Materials (BOM), and Gerber files; led coordination with PCBPower fabricators to ensure compliance with industry standards and seamless assembly
• Conducted thorough testing and validation using oscilloscopes and multimeters to verify temperature stability and controller responsiveness under variable operating conditions, ensuring high precision and robustness
• Collaborated cross-functionally with hardware and control teams, demonstrating technical leadership in hardware prototyping and thermal system design to deliver a scalable, manufacturable solution that reduced maintenance costs and improved overall system performance
Asynchronous FIFO design and Verification in verilog
Technologies: Verilog HDL, ModelSim, Gray Code Encoding, Multi-stage Synchronizers, RTL Simulation, Functional Coverage Analysis
• Engineered an 8-depth, 4-bit wide asynchronous FIFO in Verilog to enable reliable and low-latency data transfer across asynchronous clock domains, effectively mitigating metastability risks
• Applied Gray code pointer encoding combined with multi-stage synchronizer modules to ensure robust clock domain crossing (CDC), reducing synchronization latency by 15%
• Designed and implemented MSB-based pointer comparison logic for accurate full/empty detection, preventing data overflow and underflow, thereby enhancing system data integrity
• Developed comprehensive ModelSim testbenches covering asynchronous resets, varying clock frequencies, and edge cases, achieving 100% functional coverage and validating design robustness
• Collaborated closely with verification engineers to identify and resolve CDC-related glitches, optimizing pointer synchronization schemes and improving overall FIFO throughput
• Led the full project lifecycle from RTL design, simulation, to verification, demonstrating strong problem-solving skills and delivering a reusable FIFO module for multi-clock domain systems

CERTIFICATIONS

GPU Architectures and Programming
04/2025
NPTEL
Digital IC Design
04/2023
NPTEL

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