Technologies: ARM Cortex, SARADC, SDADC, COMPs, Power Management Units, PLL, SYSOSC, LCD, ADC-VREF, LDO
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Analog Layout Lead for ARM Cortex based MCUs in TI
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Responsible for area optimization, IP hands-on execution, scheduling, resource management, layout reviews and signoff for analog IPs along with guiding junior engineers
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Primary interface with global TI teams; ensured analog IP deliverables alignment across design, DFT, PD,DV and system groups, handle IP integration related issues
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Built from scratch of IPs like split cap based 4MSPS SARADC, SDADC, COMPs, Power Management Units, PLL, SYSOSC, LCD, ADC-VREF, LDO etc in 32MHz, 80MHz & 160MHz MCUs
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Responsible for analog block placement & chip level routings for multiple M0 and M33 MCUs, flagged multiple RTL bugs
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Flagged DRC ruledeck bugs w.r.t substrate isolation/yield & extraction bugs thus saving $$ in respins/test cost
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Created analog IP handoff checklist for SoC integration (there by leading to quality related automations in PD team)